Cadence. HDL Modeling in Encounter. RTL Compiler

Cadence Design Systems, Inc., 2006. — 196 p.This manual describes HDL modeling in RTL Compiler. The RTL Compiler software accepts both VHDL entities and Verilog design modules.Modeling HDL Designs
Synthesis Pragmas
Using HDL Commands and Attributes
Synthesizing Verilog Designs
Synthesizing VHDL Designs